The Device Modelling Part

of the grant

Sub 100 nm III-V MOSFETs for Digital Applications

Karol Kalna


The future challenges

The gate lengths of the complementary metal-oxide-semiconductor (CMOS) transistors which are around 40 nm in the 90 nm technology node are expected to reach sub-10 nm dimensions near the end of the current International Technology Roadmap for Semiconductors (ITRS) [1]. This aggressive transistor scaling [2] is driven by industry pressures to increase the chip density and performance at a reduced cost per function [3]. However, the scaling of the conventional metal-oxide-semiconductor field effect transistor (MOSFET) beyond the 45 nm technology node will be extremely challenging [4]. Very high channel doping concentrations and extremely thin gate oxides are needed to control the short channel effects in the nanometer conventional (bulk) MOSFET. However, high channel doping reduces carrier mobility, hampering the device performance and leading to a high band-to-band drain leakage current. This is accompanied by an unacceptably high gate leakage current through a very thin gate oxide [5]. Consequently, one is no longer able to improve the performance of the conventional MOSFET by simply increasing the gate capacitance in order to improve the gate overdrive.
Industry is actively pursuing solutions to these problems which are seen in (i) the introduction of high-κ gate dielectrics to reduce the gate leakage, and (ii) strained and new channel materials to boost device performance. Such measures may be able to extend the useful life of the conventional MOSFET for one or two generations but beyond the 45 nm technology node more radical solutions are needed. There is a consensus that at this point the bulk MOSFET will be replaced by an ultra-thin body (UTB) silicon on insulator (SOI) and/or a double-gate (DG) MOSFET architecture. Having better electrostatic integrities, such devices tolerate thicker gate oxides and low channel doping, allowing scaling to sub-10 nm without substantial loss of performance. At these scales, their performance could be further increased by the introduction of new channel, gate dielectric and gate materials. However, the transition to new device architectures and the introduction of new materials is a challenging task for industry, further emphasising the role of modelling and simulation in the areas of technology and device design. Modelling is tasked with screening the endless combinations of new device architectures and new materials to optimise performance thus cutting the cost of technology development to industry. The prediction of the behaviour of the next generation of CMOS devices will also be extremely beneficial to the design community which has to cope with an increasing number of changes to device topology and behaviour. Unfortunately, the present generation of models and simulation tools, which have been developed over the years to support the design of the conventional Si/SiO2 transistor, cannot cope with the new device architectures and materials.

The future solutions

From now on the introduction of at least one technology booster will be needed at each ITRS technology node in order to maintain the required performance of the scaled MOSFET [6]. These boosters include: Tensile and compressive strain have already been employed in the 90 nm technology node to increase transistor performance. For the forthcoming technology nodes, strain alone may not be sufficient to sustain the required performance and to compensate for the potential drive current loss associated with the introduction of high-κ gate dielectrics [10]. The introduction of high mobility channel materials such as SiGe, Ge, GaAs, InGaAs, InP and InSb is presently a hot topic of research [11]. To reduce QM tunnelling through thin gate SiO2 or oxinitride, high-κ dielectrics could be introduced into the gate stack. The use of high-κ materials allows the achievement of a similar or even lesser equivalent SiO2 thickness (EOT) at a larger physical thickness of the gate dielectric, substantially reducing the gate tunnelling current. However, a serious drawback of the high-κ MOSFET is the degradation of carrier mobility in the channel. This is partially related to the significant number of trapped and fixed interface charges, a consequence of the immaturity of the current high-κ growth technology. However, there is a fundamental mechanism reducing the channel mobility in the presence of high-κ materials: the interaction of electrons with the soft-polar optical (SO) interface phonons [10]. As the high-κ SO phonons have smaller energies when compared to those in SiO2, the electron interaction with them is not negligible; the higher the dielectric constant, the lower the soft-polar optical phonon limited mobility.


[1] International Technology Roadmap for Semiconductors (, SEMATECH (2003).
[2] R. Dennard, F. H. Gaensslen, H. N. Yu, L. Rideout, E. Bassous, and A. R. LeBlanc, IEEE J. Solid State Circuits SC-9, 256 (1974).
[3] D. J. Frank and Y. Taur, Solid-State Electron. 46, 315-320 (2002).
[4] H.-S. P. Wong, IBM J. Res. Dev. 46, 133-168 (2002).
[5] D. J. Frank, R. Dennard, E. Nowak, P. Solomon, Y. Taur, and H.-S. Wong, Proc. IEEE 89, 259-288 (2001).
[6] C. Fenouillet-Beranger, T. Skotnicki, S. Monfray, N. Carriere, and F. Boeuf, Solid-State Electron. 48, 961-967 (2004).
[7] D. J. Frank, S. E. Laux, and M. V. Fischetti, IEDM Tech. Dig. 553-556 (1992).
[8] T. Sekigawa and Y. Hayashi, Solid-State Electron. 27, 827-828 (1984).
[9] X. Huang et al., IEDM Tech. Dig. 67-70 (1999).
[10] M. V. Fischetti, D. A. Neumayer and E. A. Cartier, J. Appl. Phys. 90, 4587-4608 (2001).
[11] A. Pethe, T. Krishnamohan, D. Kim, S. Oh, H.-S. P. Wong, and K. C. Saraswat, IEDM Tech. Dig. (2006).

Copyright © karolkalna