The future challenges
The gate lengths of the complementary metal-oxide-semiconductor
) transistors which are around 40 nm in the 90 nm technology
node are expected to reach sub-10 nm dimensions near the end of the
current International Technology Roadmap for Semiconductors
]. This aggressive transistor scaling
] is driven by industry pressures to increase the chip
density and performance at a reduced cost per function [
However, the scaling
of the conventional
metal-oxide-semiconductor field effect transistor (MOSFET
the 45 nm technology node will be extremely challenging
]. Very high channel doping concentrations and extremely
thin gate oxides are needed to control the short channel effects in the
nanometer conventional (bulk) MOSFET. However, high channel doping
reduces carrier mobility, hampering the device performance and leading
to a high band-to-band drain leakage current. This is accompanied by an
unacceptably high gate leakage current through a very thin gate oxide
]. Consequently, one is no longer able to improve the
performance of the conventional MOSFET by simply increasing the gate
capacitance in order to improve the gate overdrive.
Industry is actively pursuing solutions to these problems which are seen
the introduction of high-κ gate dielectrics to
reduce the gate leakage
, and (ii) strained and new
channel materials to boost device performance
. Such measures may be
able to extend the useful life of the conventional MOSFET for one or two
generations but beyond the 45 nm technology node more radical solutions
are needed. There is a consensus that at this point the bulk MOSFET will
be replaced by an ultra-thin body (UTB) silicon on insulator
) and/or a double-gate (DG
) MOSFET architecture.
Having better electrostatic integrities, such devices tolerate thicker
gate oxides and low channel doping, allowing scaling to sub-10 nm
without substantial loss of performance. At these scales, their
performance could be further increased by the introduction of new
channel, gate dielectric and gate materials. However, the transition to
new device architectures and the introduction of new materials is a
challenging task for industry, further emphasising the role of modelling
and simulation in the areas of technology and device design. Modelling
is tasked with screening the endless combinations of new device
architectures and new materials to optimise performance thus cutting the
cost of technology development to industry. The prediction of the
behaviour of the next generation of CMOS devices will also be extremely
beneficial to the design community which has to cope with an increasing
number of changes to device topology and behaviour. Unfortunately, the
present generation of models and simulation tools, which have been
developed over the years to support the design of the conventional
transistor, cannot cope with the new device
architectures and materials.
The future solutions
From now on the introduction of at least one technology booster
will be needed at each ITRS technology node in order to maintain the
required performance of the scaled MOSFET [
]. These boosters
- the introduction of a strain and novel channel materials [
- the introduction of high-κ gate stacks [
- the introduction of metal gates [
- and the introduction of novel transistor architectures [
Tensile and compressive strain have already been employed in the 90 nm
technology node to increase transistor performance. For the forthcoming
technology nodes, strain alone may not be sufficient to sustain the
required performance and to compensate for the potential drive current
loss associated with the introduction of high-κ gate dielectrics
]. The introduction of high mobility channel materials
such as SiGe, Ge, GaAs, InGaAs, InP and InSb is presently a hot topic of
]. To reduce QM tunnelling through thin gate
or oxinitride, high-κ dielectrics could be
introduced into the gate stack. The use of high-κ materials allows
the achievement of a similar or even lesser equivalent SiO2
thickness (EOT) at a larger physical thickness of the gate dielectric,
substantially reducing the gate tunnelling current. However, a serious
drawback of the high-κ MOSFET is the degradation of carrier
mobility in the channel. This is partially related to the significant
number of trapped and fixed interface charges, a consequence of the
immaturity of the current high-κ growth technology. However, there
is a fundamental mechanism reducing the channel mobility in the presence
of high-κ materials: the interaction of electrons with the
soft-polar optical (SO) interface phonons [
]. As the
high-κ SO phonons have smaller energies when compared to those in
, the electron interaction with them is not negligible;
the higher the dielectric constant, the lower the soft-polar optical
phonon limited mobility.
] International Technology Roadmap for Semiconductors
(http://public.itrs.net/), SEMATECH (2003).
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