Karol KALNA
Professor
email: k.kalna(at)swansea.ac.uk |
room: B202, Engineering East, Bay Campus | phone: +44 (0)1792 60 6678 |
Research | PhD Students | |||
III-V MOSFETs | Device simulator | Professional CV | PhD Positions | Publications |
My research activities include physical modelling of nanoscale semiconductor transistors for digital applications using on 3D finite element ensemble Monte Carlo device simulations with integrated 2D finite element 2D Schrödinger equation solver. This research originates from my EPSRC Advanced Research Fellowship
"Modelling of Carrier Transport in Ultra Thin Body Transistors". The 3D code was used to simulate nanoscale metal contacts within the EPSRC project "Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors" in collaboration with Dr. Peter Sushko, at that time at University College London (now at Pacific Northwest National Laboratory).
I am running, jointly with Dr Antonio Martinez, a Nanoelectronic Devices Computational (NanoDeCo) Group. Our research interests include the modelling of MOSFETs including non-planar, 3D architectures as FinFETs (see below), nanosheet and nanowire FETs based on Si and III-V channels; ultra-fast pseudomorphic and metamorphic high electron mobility transistors (PHEMTs and MHEMTs) based on III-V materials; and a modelling of GaN HEMTs for RF and power applications. I was also a co-investigator for an EPSRC project on III-V MOSFETs and leading device simulations in an EU FP7 DUALLOGIC grant.
Click to enlarge Fig. 1: A 3D simulation domain of the 25 nm gate length Si SOI FinFET showing examples of 2D cross-sections for the solution of Schrödinger equation simulated by VENDES. The electron density illustrating dopants in source/drain is visualised at a high applied drain bias of 1.0 V. |
The core tools of my device modelling research are:
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The Monte Carlo simulator MC/H2F forecasted a performance of high electron mobility transistor (HEMTs) scaled into deep sub-100 nm dimensions (Fig. 3). The typical pseudomorphic HEMT simulated using Monte Carlo device simulator has a T-shaped gate; a 30-nm heavily Si-doped 4x1018 cm-3 n+ GaAs cap layer; an Al0.3 Ga0.7As etchstop layer; a 7x1012 cm-2 Si delta doped layer on top of an Al0.3 Ga0.7As spacer layer and, finally, an In0.2Ga0.8As channel. The whole device structure is grown on top of a 50-nm GaAs buffer. Click to enlarge Fig. 2: A cross-section of the proposed III-V MOSFET simulated with the MC/MOS. The finite element heterostructure ensemble Monte Carlo device simulator uses quadrilateral finite elements to depict a complex geometry of the HEMTs or MOSFETs, and accurately calculates electrostatic effects caused by the gate and recess geometry as well as the surface potential pinning. It is capable of precisely reproducing a T-shape gate and recess formation in the device. The Monte Carlo module includes electron scattering with polar optical phonons; inter- and intra-valley non-polar optical phonons; acoustic phonons; and ionized and neutral impurity scattering. In addition, alloy scattering and strain effects are considered in the InGaAs channel of the device. |
Fig. 3: A cross-section of pseudomorphic high electron mobility transistor simulated with the MC/H2F. |
PhD Thesis | SI and derived units | Numerical codes in Fortran 90 | Badminton court | Private Photos |
Copyright © karolkalna | Last modification: 8 August, 2024 |